diff -urb -x '*.1' -x '*.info' -x '*~' binutils-2.15/gas/config/tc-ppc.c binutils-2.15.mod/gas/config/tc-ppc.c
--- binutils-2.15/gas/config/tc-ppc.c	2004-05-17 12:36:11.000000000 -0700
+++ binutils-2.15.mod/gas/config/tc-ppc.c	2004-11-28 19:08:13.403326580 -0700
@@ -310,6 +310,7 @@
    sdr1           has the value 25
    srr0           has the value 26
    srr1           has the value 27
+   gqr0..7        have the values 912..919
 
    The table is sorted. Suitable for searching by a binary search.  */
 
@@ -407,6 +408,15 @@
 
   { "fpscr", 0 },
 
+  { "gqr0", 912 }, /* Gekko quantization registers */
+  { "gqr1", 913 },
+  { "gqr2", 914 },
+  { "gqr3", 915 },
+  { "gqr4", 916 },
+  { "gqr5", 917 },
+  { "gqr6", 918 },
+  { "gqr7", 919 },
+
   { "lr", 8 },     /* Link Register */
 
   { "pmr", 0 },
@@ -914,6 +924,9 @@
   /* -many means to assemble for any architecture (PWR/PWRX/PPC).  */
   else if (strcmp (arg, "any") == 0)
     ppc_cpu |= PPC_OPCODE_ANY;
+  else if (strcmp (arg, "gekko") == 0)
+      ppc_cpu = (PPC_OPCODE_CLASSIC | PPC_OPCODE_PPC
+        | PPC_OPCODE_32 | PPC_OPCODE_GEKKO);
   else
     return 0;
 
@@ -1106,6 +1119,7 @@
 -maltivec		generate code for AltiVec\n\
 -me500, -me500x2	generate code for Motorola e500 core complex\n\
 -mspe			generate code for Motorola SPE instructions\n\
+-mgekko		generate code for Gamecube Gekko\n\
 -mregnames		Allow symbolic names for registers\n\
 -mno-regnames		Do not allow symbolic names for registers\n"));
 #ifdef OBJ_ELF
@@ -1150,6 +1164,9 @@
 	  else
 	    ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
 	}
+      else if (strcmp (default_cpu, "gekko") == 0)
+        ppc_cpu |= (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32
+                    | PPC_OPCODE_GEKKO);
       else
 	as_fatal (_("Unknown default cpu = %s, os = %s"),
 		  default_cpu, default_os);
@@ -2568,8 +2585,28 @@
 
       if (need_paren)
 	{
-	  endc = ')';
 	  need_paren = 0;
+          endc = ')';
+	  if (opindex_ptr[1])
+	  {
+	    /* do check here if we have further opcodes */
+	    if (*str != endc && (endc != ',' || *str != '\0'))
+	    {
+	      as_bad(_("syntax error; found `%c' but expected `%c'"),*str,endc);
+	      break;
+	    }
+	    /* we have to move over whitespace ourselves */
+	    if (*str != '\0')
+	    {
+	      ++str;
+	      while (ISSPACE(*str))
+	      {
+		++str;
+	      }
+	    }
+	    /* now we're looking for the comma */
+	    endc = ',';
+	  }
 	}
       else if ((operand->flags & PPC_OPERAND_PARENS) != 0)
 	{
diff -urb -x '*.1' -x '*.info' -x '*~' binutils-2.15/include/opcode/ppc.h binutils-2.15.mod/include/opcode/ppc.h
--- binutils-2.15/include/opcode/ppc.h	2004-05-17 12:36:06.000000000 -0700
+++ binutils-2.15.mod/include/opcode/ppc.h	2004-11-28 19:08:13.405326179 -0700
@@ -134,6 +134,9 @@
 /* Opcode is supported by machine check APU.  */
 #define PPC_OPCODE_RFMCI	  0x800000
 
+/* Opcode is only supported by the PowerPC Gekko processor */
+#define PPC_OPCODE_GEKKO         0x1000000
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 
@@ -281,6 +284,10 @@
 /* This operand is for the DQ field in a DQ form instruction.  */
 #define PPC_OPERAND_DQ (0100000)
 
+/* This operand names a quantization register.  The disassembler
+   prints these with a leading 'gqr'.  */
+#define PPC_OPERAND_GQR (0200000)
+
 /* The POWER and PowerPC assemblers use a few macros.  We keep them
    with the operands table for simplicity.  The macro table is an
    array of struct powerpc_macro.  */
diff -urb -x '*.1' -x '*.info' -x '*~' binutils-2.15/opcodes/ppc-dis.c binutils-2.15.mod/opcodes/ppc-dis.c
--- binutils-2.15/opcodes/ppc-dis.c	2004-05-17 12:35:55.000000000 -0700
+++ binutils-2.15.mod/opcodes/ppc-dis.c	2004-11-28 19:08:13.406325979 -0700
@@ -71,6 +71,12 @@
       /* efs* and AltiVec conflict.  */
       dialect &= ~PPC_OPCODE_ALTIVEC;
     }
+  else if (info->disassembler_options
+           && strstr (info->disassembler_options, "gekko") != NULL)
+    {
+      dialect |= PPC_OPCODE_GEKKO;
+      dialect &= ~PPC_OPCODE_ALTIVEC;
+    }
   else
     dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
 		| PPC_OPCODE_COMMON);
@@ -247,6 +253,8 @@
 	    (*info->print_address_func) (memaddr + value, info);
 	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
+	  else if ((operand->flags & PPC_OPERAND_GQR) != 0)
+	    (*info->fprintf_func) (info->stream, "gqr%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_CR) == 0
 		   || (dialect & PPC_OPCODE_PPC) == 0)
 	    (*info->fprintf_func) (info->stream, "%ld", value);
@@ -312,4 +320,5 @@
   fprintf (stream, "  power4                   Disassemble the Power4 instructions\n");
   fprintf (stream, "  32                       Do not disassemble 64-bit instructions\n");
   fprintf (stream, "  64                       Allow disassembly of 64-bit instructions\n");
+  fprintf (stream, "  gekko                    Disassemble the Gamecube Gekko instructions\n");
 }
diff -urb -x '*.1' -x '*.info' -x '*~' binutils-2.15/opcodes/ppc-opc.c binutils-2.15.mod/opcodes/ppc-opc.c
--- binutils-2.15/opcodes/ppc-opc.c	2004-05-17 12:35:55.000000000 -0700
+++ binutils-2.15.mod/opcodes/ppc-opc.c	2004-11-29 11:04:24.285849054 -0700
@@ -92,6 +92,10 @@
 static long extract_ev4 (unsigned long, int, int *);
 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
 static long extract_ev8 (unsigned long, int, int *);
+static unsigned long insert_psq_gd (unsigned long, long, int, const char **);
+static long extract_psq_gd (unsigned long, int, int *);
+static unsigned long insert_psq_gx (unsigned long, long, int, const char **);
+static long extract_psq_gx (unsigned long, int, int *);
 
 /* The operands table.
 
@@ -554,8 +558,21 @@
 #define MTMSRD_L WS + 1
   { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
 
-};
+#define PSQ_DD MTMSRD_L + 1
+  { 12, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+  
+#define PSQ_WD PSQ_DD + 1
+  { 1, 15, 0, 0, 0 },
 
+#define PSQ_GD PSQ_WD + 1
+  { 10, 12, insert_psq_gd, extract_psq_gd, PPC_OPERAND_GQR },
+
+#define PSQ_WX PSQ_GD + 1
+  { 1, 10, 0, 0, 0 },
+
+#define PSQ_GX PSQ_WX + 1
+  { 10, 7, insert_psq_gx, extract_psq_gx, PPC_OPERAND_GQR }
+};
 /* The functions used to insert and extract complicated operands.  */
 
 /* The BA field in an XL form instruction when it must be the same as
@@ -1417,6 +1434,48 @@
   return ret;
 }
 
+static unsigned long
+insert_psq_gd (unsigned long insn,
+	       long value,
+	       int dialect ATTRIBUTE_UNUSED,
+	       const char **errmsg)
+{
+  if (value >= 912 && value <= 919)
+    value -= 912;
+  if (value < 0 || value > 7)
+    *errmsg = _("invalid quantization register");
+  return insn | ((value & 7) << 12);
+}
+
+static long
+extract_psq_gd (unsigned long insn,
+		int dialect ATTRIBUTE_UNUSED,
+		int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0x7000) >> 12);
+}
+
+static unsigned long
+insert_psq_gx (unsigned long insn,
+	       long value,
+	       int dialect ATTRIBUTE_UNUSED,
+	       const char **errmsg)
+{
+  if (value >= 912 && value <= 919)
+    value -= 912;
+  if (value < 0 || value > 7)
+    *errmsg = _("invalid quantization register");
+  return insn | ((value & 7) << 7);
+}
+
+static long
+extract_psq_gx (unsigned long insn,
+		int dialect ATTRIBUTE_UNUSED,
+		int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0x380) >> 7);
+}
+
 /* Macros used to form opcodes.  */
 
 /* The main opcode.  */
@@ -1696,6 +1755,10 @@
 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
 #define XUC_MASK      XUC(0x3f, 0x1f)
 
+/* A PSQ style load/store indexed */
+#define PSQX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7f))
+#define PSQX_MASK     PSQX(0x3f,0x7f)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -1786,6 +1849,7 @@
 #define PPCCHLK	PPC_OPCODE_CACHELCK
 #define PPCCHLK64	PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
 #define PPCRFMCI	PPC_OPCODE_RFMCI
+#define PPCGEKKO       PPC_OPCODE_GEKKO
 
 /* The opcode table.
 
@@ -2344,6 +2408,74 @@
 { "evdivws",  VX(4, 1222), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evdivwu",  VX(4, 1223), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 
+{ "psqlx",   PSQX(4,12),PSQX_MASK, PPCGEKKO, { FRT,RA0,RB,PSQ_WX,PSQ_GX } },  
+{ "psq_lx",  PSQX(4,12),PSQX_MASK, PPCGEKKO, { FRT,RA0,RB,PSQ_WX,PSQ_GX } },
+
+{ "psqlux",  PSQX(4,76),PSQX_MASK, PPCGEKKO, { FRT,RAS,RB,PSQ_WX,PSQ_GX } },  
+{ "psq_lux", PSQX(4,76),PSQX_MASK, PPCGEKKO, { FRT,RAS,RB,PSQ_WX,PSQ_GX } },
+
+{ "psqstx",  PSQX(4,14),PSQX_MASK, PPCGEKKO, { FRS,RA0,RB,PSQ_WX,PSQ_GX } },  
+{ "psq_stx", PSQX(4,14),PSQX_MASK, PPCGEKKO, { FRS,RA0,RB,PSQ_WX,PSQ_GX } },
+
+{ "psqstux", PSQX(4,78),PSQX_MASK, PPCGEKKO, { FRS,RAS,RB,PSQ_WX,PSQ_GX } },
+{ "psq_stux",PSQX(4,78),PSQX_MASK, PPCGEKKO, { FRS,RAS,RB,PSQ_WX,PSQ_GX } },
+
+{ "psabs",     XRC(4,264,0),XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psabs.",    XRC(4,264,1),XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psadd",     A(4,21,0),   AFRC_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psadd.",    A(4,21,1),   AFRC_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "pscmpo0",   X(4,32),X_MASK|(3<<21),	PPCGEKKO, 	{ BF, FRA, FRB } },
+{ "pscmpo1",   X(4,96),X_MASK|(3<<21),	PPCGEKKO, 	{ BF, FRA, FRB } },
+{ "pscmpu0",   X(4,0), X_MASK|(3<<21),	PPCGEKKO, 	{ BF, FRA, FRB } },
+{ "pscmpu1",   X(4,64),X_MASK|(3<<21),	PPCGEKKO, 	{ BF, FRA, FRB } },
+{ "psdiv",     A(4,18,0),   AFRC_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psdiv.",    A(4,18,1),   AFRC_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge00", XRC(4,528,0),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge00.",XRC(4,528,1),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge01", XRC(4,560,0),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge01.",XRC(4,560,1),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge10", XRC(4,592,0),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge10.",XRC(4,592,1),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge11", XRC(4,624,0),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmerge11.",XRC(4,624,1),XRA_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmr",      XRC(4,72,0), XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psmr.",     XRC(4,72,1), XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psnabs",    XRC(4,136,0),XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psnabs.",   XRC(4,136,1),XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psneg",     XRC(4,40,0), XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psneg.",    XRC(4,40,1), XRA_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psres",     A(4,24,0), AFRAFRC_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psres.",    A(4,24,1), AFRAFRC_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psrsqrte",  A(4,26,0), AFRAFRC_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "psrsqrte.", A(4,26,1), AFRAFRC_MASK,	PPCGEKKO, 	{ FRT, FRB } },
+{ "pssub",     A(4,20,0),   AFRC_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "pssub.",    A(4,20,1),   AFRC_MASK,	PPCGEKKO, 	{ FRT, FRA, FRB } },
+{ "psmadd",    A(4,29,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmadd.",   A(4,29,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmadds0",  A(4,14,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmadds0.", A(4,14,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmadds1",  A(4,15,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmadds1.", A(4,15,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmsub",    A(4,28,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmsub.",   A(4,28,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psmul",     A(4,25,0),   AFRB_MASK,	PPCGEKKO, 	{ FRT, FRA, FRC } },
+{ "psmul.",    A(4,25,1),   AFRB_MASK,	PPCGEKKO, 	{ FRT, FRA, FRC } },
+{ "psmuls0",   A(4,12,0),   AFRB_MASK,	PPCGEKKO, 	{ FRT, FRA, FRC } },
+{ "psmuls0.",  A(4,12,1),   AFRB_MASK,	PPCGEKKO, 	{ FRT, FRA, FRC } },
+{ "psmuls1",   A(4,13,0),   AFRB_MASK,	PPCGEKKO, 	{ FRT, FRA, FRC } },
+{ "psmuls1.",  A(4,13,1),   AFRB_MASK,	PPCGEKKO, 	{ FRT, FRA, FRC } },
+{ "psnmadd",   A(4,31,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psnmadd.",  A(4,31,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psnmsub",   A(4,30,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "psnmsub.",  A(4,30,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "pssel",     A(4,23,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "pssel.",    A(4,23,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "pssum0",    A(4,10,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "pssum0.",   A(4,10,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "pssum1",    A(4,11,0),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "pssum1.",   A(4,11,1),   A_MASK,	PPCGEKKO, 	{ FRT,FRA,FRC,FRB } },
+{ "dcbz_l",    X(4,1014),   XRT_MASK,	PPCGEKKO, 	{ RA, RB } },
+
 { "mulli",   OP(7),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
 { "muli",    OP(7),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
 
@@ -4373,12 +4505,19 @@
 
 { "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA0 } },
 
+
 { "stfdu",   OP(55),	OP_MASK,	COM,		{ FRS, D, RAS } },
 
+{ "psql",    OP(56),	OP_MASK,	PPCGEKKO,{ FRT,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+{ "psq_l",   OP(56),	OP_MASK,	PPCGEKKO,{ FRT,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+  
 { "lq",      OP(56),	OP_MASK,	POWER4,		{ RTQ, DQ, RAQ } },
 
 { "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
+{ "psqlu",   OP(57),	OP_MASK,	PPCGEKKO,{ FRT,PSQ_DD,RA,PSQ_WD,PSQ_GD} },  
+{ "psq_lu",  OP(57),	OP_MASK,	PPCGEKKO,{ FRT,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+  
 { "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
 { "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
@@ -4432,8 +4571,14 @@
 { "fnmadds", A(59,31,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
 { "fnmadds.",A(59,31,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
 
+{ "psqst",   OP(60),	OP_MASK,	PPCGEKKO,{ FRS,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+{ "psq_st",  OP(60),	OP_MASK,	PPCGEKKO,{ FRS,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+  
 { "stfq",    OP(60),	OP_MASK,	POWER2,		{ FRS, D, RA } },
 
+{ "psqstu",  OP(61),	OP_MASK,	PPCGEKKO,{ FRS,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+{ "psq_stu", OP(61),	OP_MASK,	PPCGEKKO,{ FRS,PSQ_DD,RA,PSQ_WD,PSQ_GD} },
+
 { "stfqu",   OP(61),	OP_MASK,	POWER2,		{ FRS, D, RA } },
 
 { "lde",     DEO(62,0), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },